This invention relates to a vector processing device or vector processor for use as a part of an electronic digital computer.
A vector processing device is for use in a high-speed digital computer in combination with a main memory in processing vectors or vector data. Each vector is an ordered set or array of elementary data.
A vector processor of the type described, is disclosed in U.S. Pat. No. 4,128,880 issued to Seymour R. Cray, Jr., and assigned to Cray Research, Inc., Wis., U.S.A. The vector processor of Cray, Jr., is effective in achieving an extremely high speed of operation.
As will later be described with reference to one of ten figures of the accompanying drawing, the vector processor comprises a plurality of vector registers according to Cray, Jr. Each vector register is for holding a vector. A vector operation arrangement may comprise a plurality of vector calculators or vector operation units, such as an arithmetic unit and a logical operation functional unit. Each vector operation unit has at least two input terminals and an output terminal for carrying out a vector operation on operand vectors received at the input terminals to produce a result vector at the output terminal. The main memory is for storing a vector as a stored vector. An input selecting arrangement is for selecting one of the vector registers as a destination register and one of the stored and the result vectors as a load vector to load the destination register with the load vector. It is to be noted that the result vector is herein referred to also as a load vector when the result vector should be stored in the destination register. An output selecting arrangement is for selecting one of the vectors held in the vector registers as a store vector for storage in the main memory. The input and the output selecting arrangements are put into operation by vector instructions of the type known in the art.
According to Cray, Jr., the output selecting arrangement must comprise an output selecting circuit. Responsive to a vector instruction indicative of a vector operation as an operation instruction, the output selecting circuit selects one of the vector registers as a destination register and two of the vector registers as source registers and couples the source registers to the input terminals of one of the vector operation units that is capable of carrying out the vector operation indicated by the vector instruction under consideration.
Since access time is indispensable for the output selecting circuit to access the source registers, the vector instruction must include areas for specifying the source registers. However, due to the included areas, the vector processor is complicated in hardware.
The number of vector registers is, for example, only eight and may not be sufficient to hold the vectors which are given by the result vectors and should be used as the operand vectors. Those of the result vectors which are not very soon used as the operand vectors, must therefore be stored in the main memory. When the vector stored in the main memory as a stored vector must be used as an operand vector, a load operation must be executed to load a pertinent one of the vector registers with the stored vector. It is known in the art that it takes a long time to carry out the load operation.